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HPCA-2022
Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings
Mike O'Connor, Donghyuk Lee, Niladrish Chatterjee, Mike Sullivan, Stephen W. Keckler.
To appear at the 28th IEEE International Symposium on High Performance Computer Architecture (HPCA), 2022.
ACM TACO
GPU Domain Specialization via Composable On-Package Architecture
Yaosheng Fu, Evgeny Bolotin, Niladrish Chatterjee, David Nellans, Stephen W. Keckler.
ACM Transactions on Architecture and Code Optimization (ACM TACO), Dec, 2021.
Coverage on The Next Platform
HPCA-2021
Need for Speed: Experiences Building a Trustworthy System-Level GPU Simulator
Oreste Villa, Daniel Lustig, Zi Yan, Evgeny Bolotin, Yaosheng Fu, Niladrish Chatterjee, Nan Jiang, David Nellans.
27th IEEE International Symposium on High Performance Computer Architecture (HPCA), Seoul, S. Korea, 2021.
ISPASS-2021
Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures
Atefeh Mehrabi, Donghyuk Lee, Niladrish Chatterjee, Daniel J. Sorin, Benjamin C. Lee, Mike O'Connor.
22nd IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2021.
SC-2019
Near-Memory Data Transformation for Efficient Sparse Matrix Multi-Vector Multiplication
Daichi Fujiki, Niladrish Chatterjee, Donghyuk Lee, Mike O'Connor.
32nd IEEE/ACM International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), Denver, USA, 2019.
ISPASS-2019
DeLTA: GPU Performance Model for Deep Learning Applications with In-Depth Memory System Traffic Analysis
Sangkug Lym, Donghyuk Lee, Mike O'Connor, Niladrish Chatterjee, Mattan Erez.
20th IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Madison, USA, 2019.
SIGMETRICS-2018
What Your DRAM Power Models are Not Telling You: Lessons from a Detailed Experimental Study
Saugata Ghose, Abdulla Giray Yaglicki, Raghav Gupta, Donghyuk Lee, Kais Kudrolli, William X. Liu, Hasan Hassan, Kevin K. Chang, Niladrish Chatterjee, Aditya Agrawal, Mike O'Connor, Onur Mutlu.
Proceedings of the ACM on Measurement and Analysis of Computer Systems (SIGMETRICS), Irvine, USA, 2018.
HPCA-2018
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
Minsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Youngeun Kwon, Stephen W. Keckler.
24th IEEE International Symposium on Higher Performance Computer Architecture (HPCA), Vienna, Austria, 2018.
HPCA-2018
Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction
Donghyuk Lee, Mike O'Connor, Niladrish Chatterjee.
24th IEEE International Symposium on Higher Performance Computer Architecture (HPCA), Vienna, Austria, 2018.
Best Paper Nominee
MICRO-2017
Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems
Mike O'Connor*, Niladrish Chatterjee*, Donghyuk Lee, John Wilson, Aditya Agrawal, Stephen W. Keckler, William J. Dally.
50th IEEE/ACM International Symposium on Microarchitecture (MICRO), Boston, USA, 2017.
*equal contributors
SC-2017
Toward Standardized Near-Data Processing with Unrestricted Data Placement for GPUs
Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Kevin Hsieh.
30th IEEE/ACM International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), Denver, USA, 2017.
SIGMETRICS-2017
Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms
Kevin K. Chang, Abdulla Giray Yaglikci, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hassan Hassan, Onur Mutlu.
Proceedings of the ACM on Measurement and Analysis of Computer Systems (SIGMETRICS), Champaign-Urbana, USA, 2017.
HPCA-2017
Architecting an Energy-Efficient DRAM System For GPUs
Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, William J. Dally.
23rd IEEE International Symposium on Higher Performance Computer Architecture (HPCA), Austin, USA, 2017.
Coverage on The Next Platform
ISCA-2016
Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems
Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, Onur Mutlu, Stephen W. Keckler.
43rd ACM/IEEE International Symposium on Computer Architecture (ISCA), Seoul, S. Korea, 2016.
ISPASS-2016
Addressing Service Interruptions in Memory with Thread-to-Rank Assignment
Manjunath Shevgoor, Rajeev Balasubramonian, Niladrish Chatterjee, Jung-Sik Kim.
17th IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Uppsala, Sweden, 2016.
Best Paper Award
MEMSYS-2016
CLARA: Circular Linked-List Refresh Architecture
Aditya Agrawal, Mike O'Connor, Evgeny Bolotin, Niladrish Chatterjee, Joel Emer, Stephen W. Keckler
International Symposium on Memory Systems (MEMSYS). Washington D.C., USA, 2016.
MEMSYS-2015
Anatomy of GPU Memory System for Multi-Application Execution
Adwait Jog, Onur Kayiran, Tuba Kesten, Ashutosh Pattnaik, Evgeny Bolotin, Niladrish Chatterjee, Stephen W. Keckler, Mahmut T. Kandemir, Chita R. Das
International Symposium on Memory Systems (MEMSYS). Washington D.C., USA, 2015.
SC-2014
Managing DRAM Latency Divergence in Irregular GPGPU Applications
Niladrish Chatterjee, Mike O'Connor, Gabriel H. Loh, Nuwan Jayasena, Rajeev Balasubramonian
27th IEEE/ACM International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), New Orleans, USA, 2014.
MICRO-2013
Quantifying the Relationship between the Power-Delivery Network and Architectural Policies in 3-D Stacked Memory Devices
Manjunath Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Aniruddha Udipi
46th ACM/IEEE International Symposium on Microarchitecture (MICRO). Davis, USA, 2013.
MICRO-2012
Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access
Niladrish Chatterjee, Manjunath Shevgoor, Rajeev Balasubramonian, Al Davis, Zhen Fang, Ramesh Illikkal, Ravi Iyer
45th ACM/IEEE International Symposium on Microarchitecture (MICRO). Vancouver, Canada, 2012.
HPCA-2012
Staged Reads: Mitigating the Impact of DRAM Writes on DRAM Reads
Niladrish Chatterjee, Rajeev Balasubramonian, Naveen Muralimanohar, Al Davis, Norm Jouppi
18th International Symposium on High Performance Computer Architecture (HPCA). New Orleans, USA, 2012.
ASPLOS-2010
Micro-pages: Increasing DRAM Efficiency with Locality-Aware Data Placement
Kshitij Sudan, Niladrish Chatterjee, Dave Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis
15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Pittsburgh, USA, 2010.
ISCA-2010
Rethinking DRAM Design and Organization for Energy-Constrained Multi-cores
Aniruddha Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norm Jouppi
37th ACM/IEEE International Symposium on Computer Architecture (ISCA). St. Malo, France, 2010.
SIGGRAPH'14
Why Graphics Programmers Need to Know About DRAM
Erik Brunvand, Daniel Kopta, Niladrish Chatterjee
Course at the 41st International Conference and Exhibition on Computer Graphics and Interactive Techniques, Vancouver, Canada, 2014.
WACAS-2014
Exploring a Brink-of-Failure Memory Controller to Design an Approximate Memory System
Meysam Taassori, Niladrish Chatterjee, Ali Shafiee, Rajeev Balasubramonian
1st Workshop on Approximate Computing Across the System Stack (WACAS),held in conjunction with ASPLOS-2014, Salt Lake City, USA, 2014.
WEED-2013
Understanding the Role of the Power Delivery Network in 3D-Stacked Memory Devices
Manjunath Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian
5th Workshop on Energy-Efficient Design (WEED), held in conjunction with ISCA-2013, Tel Aviv, Israel 2013.
UUCS-12-002
USIMM: the Utah Simulated Memory Module. A Simulation Infrastructure for the JWAC Memory Scheduling Competition
Niladrish Chatterjee, Rajeev Balasubramonian, Manjunath Shevgoor, Seth H. Pugsley, Aniruddha N. Udipi, Ali Shaifei, Manu Awasthi, Kshitij Sudan, Zeshan Chishti
University of Utah Technical Report, 2012.
UCAS-2009
Optimizing a Multi-Core Processor for Message Passing Workloads
Niladrish Chatterjee, Seth Pugsley, Josef Spjut, Rajeev Balasubramonian
5th Workshop on Unique Chips and Systems, held in conjunction with ISPASS-2009, Boston, USA, 2009.